This post is a guide to the architectural layout and usage of flash memory. We will be looking at the Infineon Aurix TriCore platform here for reference. Every manufacturer has its lingo. Always refer to your controller datasheet for details.
The NVM Subsystem
In Aurix, the flash memory and related components are collectively called the Non Volatile Memory Subsystem. It comprises of the
- Data Memory Unit (DMU)
- Program Flash Interface (PFI)
- Non Volatile Memory Module comprising of the
- Flash Standard Interface (FSI)
- Program and Data Flash memories and
- Program Flash Read Write buffer
Get the full resolution image here on Github.
Data Memory Unit (DMU):
- Controls command sequences executed on all program and data flash memories.
- Has separate command sequence interpreter for HSM and Host Cores.
Program Flash Interface (PFI):
- Connects a PFLASH bank to a CPU core.
Flash Standard Interface (FSI):
- Executes erase, program and verify operations on all the flash memories.
Program Flash (PFLASH):
- It is used by the application to store program code and data constants.
- Divided into one or more banks, each connected to a CPU.
Data Flash (DFLASH):
- The Data Flash Module is used to emulate EEPROM and store data.
- This is supported for both the host core and HSM core.
- DFLASH read accesses are relatively slow compared to PFLASH accesses.
- Data Flash Module also contains regions to store configuration data
- User Configuration Blocks (UCBs), and
- Configuration Sector (CFS), which is not accessible by the user.
Definition of Terms
The Non Volatile Memory modules use the following terminology:
Flash Operation Terms
Erasing: The erased state of a Flash cell is logical ‘0’. Forcing a cell to this state is called “erasing”. Complete Flash sectors are erased. All the Flash cells in this area incur one “cycle” that counts for the “endurance”.
Programming: The programmed state of a Flash cell is logical ‘1’. Changing an erased Flash cell to this state is called “programming”. Programming bits within a page to a logic ‘1’ occurs concurrently.
Retention: This is the time during which the data of a flash cell can be read reliably. The retention time is a statistical figure that depends on the operating conditions of the device (e.g. temperature profile) and is affected by operations on other Flash cells in the same wordline and physical sector. With an increasing number of program/erase cycles (see endurance), the retention is lowered.
Endurance: As described above, the data retention is reduced with an increasing number of program/erase cycles. The maximum number of program/erase cycles of each Flash cell is called “endurance”. As retention, it is a statistical figure that depends on operating conditions, the use of the flash cells and the required quality level.
Flash Structure Terms
Flash Module: A module that contains a Non Volatile Memory (NVM) with its own digital control logic.
Bank: A “Flash module” contains separate “banks”. In the PFLASH, there are one or more PFp banks, and in the DFLASH, there are one or more banks. “Banks” support concurrent operations with some limitations due to common logic. It is split into sectors:
Physical Sectors: One physical area of memory is isolated from another area of memory.
Logical Sectors: A physical sector is further separated into logical sectors. A logical sector is a group of wordlines for PFLASH and DFLASH, and a single wordline for UCB. A logical sector can be erased with a single operation. The plain term “sector” means “logical sector”.
Page: A page is an aligned group of data doublewords plus an ECC extension. It is the smallest unit that can be programmed. — PFLASH: 4 data double words (32 bytes) plus 22-bit ECC extension. — DFLASH: 1 data doubleword (8 bytes) plus 22-bit ECC extension.
Wordline: An aligned group of bytes: — PFLASH: 1024 bytes. — DFLASH: 512 bytes in single-ended mode and 256 bytes in complement sensing mode.
Program Burst: The maximum amount of data that can be programmed with one command. The programming throughput is higher than for programming single pages.
- PFLASH: 8 pages (256 bytes).
- DFLASH: 4 pages (32 bytes).
How to handle Flash Memory in software
Reading Flash Memory
- Reading Flash Memory is a lot easier than writing to it.
- All read accesses to Flash are memory-mapped reads. Therefore, it does not need to go through the DMU and FSI of the NVM subsystem.
- In code, reading a flash memory can be as simple as pointing to a location and getting the data.
- To simplify reading larger amounts of data, one can implement a simple memcpy function.
- Make it safe and reliable as per any coding guideline that you are following, MISRA-C, CERT etc.
- Run the code quality checks on this using any tools like QAC or Polyspace.
- Use this for all memory read operations.
Writing flash memory
- Writing to flash memory is a little complicated.
- Before you can write to flash memory, it needs to be erased. This is the physical nature of flash memory.
- Erase operations are done at block levels. In our case, logical sector level. For PFlash 16kb memory size or 4kb/2kb in case of DFlash.
- Write operations happen at page scales, for PFlash 32 bytes or 8 bytes in the case of DFlash.
- All write and erase operations go through the DMU and FSI of the NvM Subsystem.
- When the software requests a erase or write function, specific command sequences are sent to DMU.
- These commands are written to the registers of DMU. DMU then sends instructions to FSI.
- FSI operates over the flash memory to perform those operations. There are restrictions on the page boundary, logical sector boundary, physical sector boundary or bank boundaries in the drivers. Be sure to be aware of them when working with the erase and write operations.
- Silicon vendors provide flash memory driver libraries for their chips. A typical flash erase function would look like this.